This invention relates to timing circuits.
It is common to use a resistive-capacitive network in electronic timing circuits, in which a potential derived from the charging of a capacitor through a resistive network causes a threshold or switching device to respond when this potential reaches a predetermined threshold.
In order to ensure that a timing circuit operates in a fail-safe manner, it is desirable that in the event of failure of the timing capacitor, either by short circuiting or open circuiting, the threshold potential of the switching device is not exceeded. The usual known type of capacitive timing circuit does not meet with this criterion in that failure of the capacitor can result in the timing of an interval, albeit shorter than the designed interval, which in the context of a signalling system could be potentially dangerous.
An object of the present invention is to provide a timing circuit including a timing capacitor in which failure of the capacitor results in effective disablement of the timing circuit, so that the circuit as a whole fails to safety.